1. Field of the Invention
The present invention relates to a power amplifier
2. Related Art
In the conventional portable radio terminals, a large number of power amplifiers using a compound semiconductor in a final amplification stage are used. As the CMOS process becomes finer, however, efforts are continued to implement not only the baseband circuit but also the high frequency analog circuit at the front end by using CMOS circuits. Partially, they are already commercially available. As compared with the compound semiconductor process, the CMOS integrated circuit process has a feature that it is comparatively inexpensive per unit area.
The power amplifier is demanded to have high power efficiency in order to implement long time battery drive for the portable terminal. On the other hand, as higher data transmission rates are strongly demanded, more complicated modulation systems tend to be introduced in communication systems and as a result, high linearity is required for the power amplifier.
In case the power amplifier is formed of only one final-stage transistor, and the power amplifier is driven with small amplitude, the linearity between the input signal and the output signal is better, but the power efficiency is lower. On the other hand, if the power amplifier is driven with large amplitude, the power efficiency is higher, but the amplitude of the output signal is saturated, resulting in the worse linearity to become worse. In other words, there used to be a problem in a power amplifier that the efficiency and the linearity were in relation for trade-off each other.
As means to implement a power amplifier having a high power efficiency, a method in which a power amplifier is divided into a plurality of saturation amplifying units connected in parallel and synthesizing their outputs is proposed (for example, see JP-A 2005-86673 (KOKAI)). According to the power amplifier disclosed in JP-A 2005-86673 (KOKAI), a plurality of amplifying units are provided and driven in an efficient saturation region in each of the amplifying units. In order to change the amplitude of the output power, the number of driven amplifying units is controlled. In implementing the linearity, therefore, it is necessary to provide a controller separately to turn on/off the individual amplifying units. It is possible to integrate such a controller on the same semiconductor chip with the same amplifying units by using digital logic circuits using the CMOS process. A relation between amplitude a(t) of a modulation signal and the number n of saturation amplifying units turned on by the controller is indicated in JP-A 2005-86673 (KOKAI). A relation between an amplitude of a modulation signal and an amplitude of an output signal obtained as a result of the above-described on/off control is shown in FIG. 10 in JP-A 2005-86673 (KOKAI). It is also disclosed that saturation output powers of the individual amplifying units in the amplifying units need not be necessarily equal and the amplifying units can also be implemented by providing the individual amplifying units with relations of powers of 2. Owing to such a configuration, an amplified signal having less distortion is obtained even in a non-constant amplitude signal (a signal which is not constant in amplitude).
If the technique described in JP-A 2005-86673 (KOKAI) is implemented, it should be possible to solve the problem in the conventional power amplifier, i.e., relation of trade-off between the power efficiency and the linearity. As a matter of course, for implementing the above-described technique in practical use, however, it becomes necessary to solve some extremely serious difficulties.
First, in the first embodiment in JP-A 2005-86673 (KOKAI), it is described that an F-class amplifier utilizing FETs can be used as an example of the saturation amplifying unit. As compared with an A-class amplifier or a B-class amplifier, the F-class amplifier has a feature that high power efficiency is obtained. If it is attempted to implement the individual saturation amplifying units by using the F-class amplifiers, it is necessary to connect an inductance between a power supply voltage VDD and a FET and connect a transmission line having a quarter wavelength between the FET and an output terminal as described in a paper (Alireza Shirvani, David K. Su, and Bruce A. Wooley, “A CMOS RF Power Amplifier With Parallel Amplification For Efficient Power Control”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 6, JUNE 2002) cited in JP-A 2005-86673 (KOKAI). If such inductance and transmission line are formed on the same substrate as the FET, an extremely large area becomes necessary. Because passive elements such as the inductance and the transmission line formed on the semiconductor substrate needs an area larger than that of the FET itself.
In JP-A 2005-86673 (KOKAI), the F-class amplifier is implemented by using the CMOS process. The advantage of using the CMOS process is that the process cost per unit area is lower than that with a compound semiconductor such as GaAs. If as many passive parts such as inductances and transmission lines as the number of saturation amplifying units are necessary, however, the chip area occupied by the passive parts is also compelled to become extremely large, because JP-A-2005-86673 is implicitly based on the assumption that a large number of amplifying units enough to ensure the linearity are provided. This is contradictory to the original object that the CMOS process is used to implement inexpensive amplifiers.
Secondly, if there is the above-described problem, i.e., if it is not rational in the cost aspect to provide many inductors and transmission lines in the individual amplifying units, then another possible choice is that passive parts are not provided in each individual amplifying units. It is conceivable to adopt a method of forming each of individual amplifying units of only active parts (FETs) which can be reduced in size as small as possible and instead ensuring the impedance-matching with the output terminal on the output unit side. In a different configuration example of an output power synthesizing circuit described in JP-A 2005-86673 (KOKAI), a plurality of parallel reactance elements are provided in the output power synthesizing circuit and it is attempted to achieve impedance matching depending upon the number of saturation amplifying units in use by changing over the parallel reactance elements with switches in response to a signal supplied from an amplitude controller.
Even if impedance matching should be implemented between each amplifying unit and the output terminal by using the above-described method, however, it becomes necessary to provide a plurality of reactance elements in the output power synthesizing circuit also in this case. Eventually, there is only difference between providing passive elements in the saturation amplifying units and providing the passive elements in the output compounding circuit. There is no change in that a large number of passive elements are needed, i.e., a large area is needed as a result.
In summary of the conventional art, if the single F-class amplifier is used and only a constant-amplitude signal is amplified in the saturation region, extremely high power efficiency can be obtained. If it is attempted to implement a system in which the amplifier is divided into a plurality of saturation amplifying units to use as an amplifier having a non-constant amplitude and the selected number of amplifying units is controlled by a digital logic circuit, however, a number of passive parts is necessary, and occupy a large chip area. Eventually, therefore, it is not reasonable in the cost aspect.